1. Field of the Invention
The present invention relates to a PLL frequency generator (phase-locked loop). The invention relates furthermore to a transmitting/receiving device and to an integrated circuit with a PLL frequency generator of this type.
2. Description of the Background Art
The invention falls within the field of telecommunications. It falls particularly within the field of PLL frequency generators, with whose help transmitting/receiving devices in telecommunication systems access spectrally spaced carrier frequency channels. Such PLL frequency generators derive an output signal with a settable target frequency from a highly precise reference signal and provide it as a local oscillator signal for receiver-side down-mixing of the incoming signal and/or for transmitter-side up-mixing. The settable target frequency can be selected hereby from a group of predefined target frequency values, the so-called frequency raster.
If the target frequency values each correspond to an integer multiple of the frequency of the reference signal (“reference frequency”), the frequency of the output signal can be divided in the feedback branch of the frequency generator by an integer divisor. Because of phase jitter, at the target frequency, the spectrum of the output signal of such an “integer-N” PLL frequency generator has a surrounding interference part, which determines the signal/noise ratio of the output signal, in addition to the desired spectral line.
However, if, for example, the minimum spacing between two neighboring target frequency values is smaller than the reference frequency, a frequency division by a non-integer divisor is necessary in the feedback branch of the frequency generator. Frequency divisions of this type are typically effected by switchable frequency dividers (multi-modulus divider, MMD), which in each case at times perform frequency divisions by different integer divisor values, in order to achieve the necessary non-integer frequency division within a time average. The switching between different integer divisor values, however, causes an additional time-variant periodic phase error in the frequency-divided signal and thereby another interference part in the spectrum of the output signal in the form of spectral lines. Without further measures to compensate for the additional phase error, the output signal of this type of “fractional-N” PLL frequency generator, therefore, has a lower signal/noise ratio than a corresponding integer-N PLL frequency generator or a fractional-N PLL frequency generator operated in the integer mode. On the receiver side, such spectral lines lead to undesirable secondary headends.
U.S. Pat. No. 6,064,272 discloses a fractional-N PLL frequency generator, which has a phase compensation circuit, connected downstream to the switchable frequency divider, in the feedback branch. This phase compensation circuit with use of delay lines containing a variable plurality of delay elements provides a total of four different delayed variants of the frequency-divided signal, from which one is selected by a control circuit, which is controlled by an accumulator. Furthermore, a tuning circuit (“on-chip tuning circuit”) is provided with additional delay elements, which generate a control voltage for the delay elements.
A disadvantage here is that the interfering part, caused by the fractional-N division, in the spectrum of the output signal is insufficiently suppressed and therefore the signal/noise ratio is relatively small. Additional interference parts result from the switching between delay lines. It is a disadvantage, furthermore, that the realization cost and the energy consumption of the phase compensation circuit and the tuning circuit at higher frequency resolutions (spacing between two neighboring target frequency values considerably smaller than the reference frequency) and/or at higher target frequency values, for example, in the GHz range increase drastically, and implementation of the frequency generator is therefore uneconomic or virtually no longer possible.